Tcl, Python, Perl, routing, floorplanning, UPF, RTL-to-GDSII execution, Physical Verification, automated design methodologies, LVS closure methodologies, Ir, Placement, CTS, signoff, Sta, low-power design strategies, ECO flows, physical signoff, CPF, Synthesis, Si, EM analysis, DRC

static timing analysis, Floor Planning, Synthesis, Makefile scripting, physical design CAD flow, physical design verification, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus