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Hiring Alert | Senior Analog Layout Design Engineers / Leads

Greetings from Eximietas Design!

We are actively hiring Senior Analog Layout Design Engineers / Leads with 8–12 years of experience to join our growing VLSI team.

Location: Bengaluru

Notice Period: Immediate joiners preferred

Preferred Hands On: TSMC 3nm & SERDES

Key Skills & Requirements:

Strong expertise in lower FINFET technology nodes (TSMC 3nn & SERDES preferred)

Experience in IR drop, Electromigration (EM), self-heating, RC delay, and parasitic capacitance optimization

Good understanding of layout impact on circuit performance (speed, area, power, etc.)

Ability to deliver high-quality layouts under tight design constraints

Hands-on experience with CADENCE / SYNOPSYS layout tools and flows

Scripting knowledge (PERL / SKILL) is an added advantage

Strong communication skills and experience working with cross-functional teams

If you're interested or know someone suitable, please share your updated resume at:

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+91 8088969910

Referrals are highly appreciated.

Looking forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!

Regards,

Maruthy Prasaad

Talent Associate – VLSI Manager

Eximietas Design | Visakhapatnam