Spi, DDR, I2c, Python, Usb, Uart, Shell Scripting, Perl, Ethernet, Tcl, Cadence Xcelium, Functional Checkers, Uvm, Scoreboards, Functional Coverage, Verdi, UCIe, systemverilog, Siemens QuestaSim, Synopsys VCS, Axi, MIPI, Constrained Random Verification, DVE, APB, CXL, AHB

C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND

Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Perl, Python, Tcl, timing calibration, Uvm, DDR5 LPDDR5 verification, error handling, systemverilog, SVA, functional coverage, power-management

Emulation, Code coverage and coverage closure, Post-silicon validation, ASIC SoC Design Verification, PCIe protocol verification, SoC IP-level testbench development and integration, PCIe Verification IP, Functional coverage, SystemVerilog UVM, Assertions, formal verification

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

System Verilog, Tcl Scripting, SMMU, Uvm, assertion-based verification, UPF, formal verification, Axi, power-aware verification, coverage-driven testing, SVA, Synopsys Mentor VIPs, CXL 1.1 2.0 3.0, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, Coresight architecture, CHI protocols

C, Verilog, Scripting, coverage closure, verification flows, AI-assisted workflows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog