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Bengaluru, India

Skills:

PerlPythonTclSkillCalibre PVSmixed-signal layoutCadence Virtuoso

Early Applicant
Bengaluru, India

Skills:

PerlPythonTclprimetimeCadence InnovusEM analysisPhysical VerificationSignal IntegrityStarRCTiming Closurelow-power design techniquesSynopsys ICC2

Early Applicant
Bengaluru, India

Skills:

pythonPerlSystem Verilogtest plans for DDR LPDDR IP verificationDDR-IO verificationdebug and problem solvingLPDDR JDEC specificationssystem verilog programmingcoverage driven verification methodologyUvm

Early Applicant
Bengaluru, India

Skills:

SpiDDRI2cPythonUsbUartShell ScriptingPerlEthernetTclCadence XceliumFunctional CheckersUvmScoreboardsFunctional CoverageVerdiUCIesystemverilogSiemens QuestaSimSynopsys VCSAxiMIPIConstrained Random VerificationDVEAPBCXLAHB

Early Applicant
Bengaluru, India

Skills:

VerilogVHDLsimulation debuggingDO-254traceability validation methodologiescoverage-driven verificationsystemverilog

Early Applicant
Bengaluru, India

Skills:

CPciePerlPythonTclONFILPDDRNAND

Early Applicant
Bengaluru, India

Skills:

PerlVerilogPythonCadence IncisiveXceliumcomplex testbenchesUvmsystemverilogSynopsys VCSRTL design conceptsVHDLformal verificationverification environmentsModelsim

Early Applicant
Bengaluru

Skills:

Automated TestingScripting LanguagessystemverilogUvmVerification PlanningTestbench DevelopmentFunctional CoverageDebugging SkillsSignal ProcessingFPGA Verification

Early Applicant
Bengaluru, India

Skills:

PerlPythonTest plan developmentLow power verification methodsFPGA emulator software environmentsEmulation platformsUvmTransaction level modellingsystemverilogDSP instruction set architecturesIndustry standard I/O interfacesObject-oriented designAMBA bus protocolsRTL development environmentsBaremetal processor environmentsVerification methodologiesFPGA and emulation platform knowledgeFormal verification methodsUPF based low power verificationHardware description languages

Early Applicant
Bengaluru, India

Skills:

Soc ArchitectureSystem Verilogscoreboardingdigital design fundamentalsUVM methodologyASIC SoC functional verificationSoC-level verificationconstrained-random stimulusassertionsfunctional coverageSVAperformance verification

Early Applicant
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