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Showing 10 jobs
Skills:
Perl, Python, Tcl, Skill, Calibre PVS, mixed-signal layout, Cadence Virtuoso
Skills:
Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2
Skills:
python, Perl, System Verilog, test plans for DDR LPDDR IP verification, DDR-IO verification, debug and problem solving, LPDDR JDEC specifications, system verilog programming, coverage driven verification methodology, Uvm
Skills:
Spi, DDR, I2c, Python, Usb, Uart, Shell Scripting, Perl, Ethernet, Tcl, Cadence Xcelium, Functional Checkers, Uvm, Scoreboards, Functional Coverage, Verdi, UCIe, systemverilog, Siemens QuestaSim, Synopsys VCS, Axi, MIPI, Constrained Random Verification, DVE, APB, CXL, AHB
Skills:
Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog
Skills:
C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND
Skills:
Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim
Skills:
Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification
Skills:
Perl, Python, Test plan development, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, Transaction level modelling, systemverilog, DSP instruction set architectures, Industry standard I/O interfaces, Object-oriented design, AMBA bus protocols, RTL development environments, Baremetal processor environments, Verification methodologies, FPGA and emulation platform knowledge, Formal verification methods, UPF based low power verification, Hardware description languages
Skills:
Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, UVM methodology, ASIC SoC functional verification, SoC-level verification, constrained-random stimulus, assertions, functional coverage, SVA, performance verification
