Soc, Verilog, Bus architectures, Logic synthesis for RTL code performance and power, Tape outs and bring up support, systemverilog, RTL design concepts, Memory hierarchies, Digital logic design principles, Accelerators, Processor design, Design implementation and integration of chassis subsystems, Arithmetic units, Low-power design

Synthesis, multi-clock designs, formal verification, ECO fixes, SoC clocking reset architecture, Verilog System-Verilog, Logic design RTL coding, SoC design and integration, asynchronous interfaces