Physical Synthesis, Critical-path SPICE simulation, floorplanning, Timing analysis and closure, ECO implementation, Timing sign-off methodologies, Placement Routing, Physical design sign-off, Timing Constraints, RTL-to-GDSII physical implementation flow, Power optimization and convergence, Full-chip timing closure, PPA optimization

Perl, Verilog, Python, Tcl, Signoff, Formal equivalence, IP integration, Full-chip aspects, Timing convergence, Physical Design, VHDL, Low Power Checks, Timing Verification

Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification

routing, Tcl Scripting, Shell scripting, Python, Perl, MCMM setup hold OCV AOCV POCV, CTS, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Power Planning, post-route optimization, IR Drop, STA timing closure, RTL-to-GDSII Physical Design flow, floorplanning, EM Signal Integrity, signoff, Physical Verification, Eco, DRC, Placement, Synopsys ICC2

Scripting, EMIR Signoff flow, In-rush current profiles, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving