hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, device physics, Low power design implementation

redhawk , Tcl, Perl, VSLP, Synthesis, ICC, Logic equivalence checking, Low Power checking, Calibre, Power signal integrity, Physical Design Verification, SDC clean up, Place And Route, DRC, Physical Design, SOC design, Mixed signal block integration, Dc, Timing Closure, LVS, Pt, STA timing, Deep sub-micron designs, Formality, Manufacturability