Verilog, Gdb, Perl, Python, SV-UVM, e-specman, SV, Indago, Cadence, Verification fundamentals

Verilog, Python, Perl, Gdb, SOC design, Indago, Cadence

C, Git, Shell, Perl, Python, Tcl, Xilinx FPGA, Siemens Veloce, Cadence Zebu, Palladium, Uvm, systemverilog, Vivado, SVA

code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

C, Debugging, Shell, Verilog, Tcl, System Verilog, Python, Perl, assertions, directed and constrained random methodologies, Uvm, Metric Driven Verification, formal verification methodologies

C, Debugging, Soc Architecture, Perl, Verilog, Python, CPU architecture, AMBA protocols, systemverilog, Emulation, Simulation, Verification fundamentals, Assembly