Electromigration (EM, Tcl, Python, Perl, Automation Frameworks, Physical Design and Methodology, Timing Closure, Fusion Compiler, Synopsys DSO.ai, Sub-3nm device physics, primetime, Dynamic IR drop, Crosstalk challenges, Flows-as-Code, Standard Cell SRAM library architectures, Tape-out experience with TSMC N3, CPU micro-architecture, Cerebrus, IC Compiler II, Synopsys Fusion Design Platform

Placement and Optimization, Adaptive power management techniques, Advanced low-power architectures, Signal Integrity Analysis, Leakage optimization and dynamic power reduction, ASIC SoC physical design, Floor planning and Partitioning, Routing and Congestion Analysis, UPF CPF-based low-power implementation flows, Power gating and retention strategies, Low-power verification and signoff methodologies, Power Planning, Timing Closure, Clock gating methodologies, Physical Verification and Signoff