ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting

redhawk , Innovus, primetime, Synthesis, Physical Design, tapeout

Tcl Scripting, Perl, Python, floorplanning, STA timing analysis, PVT analysis, IR EM-related issues, timing ECOs, Cadence Innovus, signoff, Signal Integrity, congestion, CTS routing optimization, full-chip physical design, Timing Closure, setup hold violations, Placement, MMMC SDC constraints, PPA optimization

synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

redhawk , Voltus, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Synopsys ICC2, Tempus, signoff tools

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management