routing, Tcl Scripting, Shell scripting, Python, Perl, MCMM setup hold OCV AOCV POCV, CTS, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Power Planning, post-route optimization, IR Drop, STA timing closure, RTL-to-GDSII Physical Design flow, floorplanning, EM Signal Integrity, signoff, Physical Verification, Eco, DRC, Placement, Synopsys ICC2

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

virtualization, Memory Management, Perl, Python, System Verilog, IP Sub System design verification, Functional Coverage, Trackers, Assertion, Checkers, HW-SW debug, Uvm, power management fundamentals, coherency protocols, DV test bench, Scoreboards, Post-Silicon bring-up, Virtual Memory concepts

gui test automation , Qt, Version Control, Embedded Testing, JIRA, Squish, Python, bus communications, Microcontroller Programming, QA best practices, Electrical Engineering, hardware debugging, SmartBear Test Complete

Java, Sql, Scalability, Docker, Fault Tolerance, Python, Kubernetes, embeddings, vector search, AI orchestration frameworks, agentic AI, LLMs, cloud native architectures, production-grade observability, Go, vector databases, semantic retrieval, Distributed System Design, agent based architectures, NoSQL data stores, CI/CD pipelines

Nvme, Jtag, Storage, Graphics and Display, PCIe Gen4, Logic Analyzers, USB Networking, Post Silicon Validation, Oscilloscopes, Debug Tools, Platform Debug, Memory Training, Customer Engagement, Firmware Traces, Debug Methodologies, Crash Dump Analysis, Python Automation Frameworks, RAS Technologies, Platform Security, DDR5, DDR4, Protocol Analyzers, Silicon-to-System Interactions

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout