Perl, Python, Sequencers, Agents, Checkers, Uvm, Functional coverage, systemverilog, Assertions, Coverage models, Verilog-AMS, Verification methodology, Scoreboards, Monitors, Constrained random techniques, Verilog-A

C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND

arm architecture , Random Instruction Sequences (RIS) tool, Assembly language (ASM), C, C++, Software Design, Hardware Design Verification, EDA Tools, CPU micro-architecture

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Perl, Python, Tcl, Siemens Calibre, PERC, Calibre Interactive, TVF, Cadence Pegasus, EDA visualizer, LVS, CalibreDRV, Calibre DesignRev scripting, DRC, Tk, design for manufacturing, Cadence Virtuoso, SVRF

Aes, Perl, Python, Tcl, AES-XTS, MACsec, Uvm, SVA, systemverilog

C, Automation Frameworks, Python, power management, RTL simulation, Emulation, debug methodologies, regression infrastructure, AMBA protocols, NoC transactors, Uvm, systemverilog, coverage closure, verification infrastructure, protocol checkers

C, Perl, Verilog, Shell scripting, Python, Tcl, EDA toolkits, UVM assertions, SVA, systemverilog

protocol stack , Gerrit, Networking, Qos, Ip Routing, Python, Java, Bash, Jenkins, Git, Linux, Integration, Lte, switching, latency, QoE, CI CD, system-level verification, traffic generation, KPIs, throughput, Deployment, Resource Utilization, 5G New Radio NR, Channel emulators, Troubleshooting, RAN architecture, Test Tools, Performance Analysis

Verilog, Gdb, Perl, Python, SV-UVM, e-specman, SV, Indago, Cadence, Verification fundamentals