Electromigration (EM, Tcl, Python, Perl, Automation Frameworks, Physical Design and Methodology, Timing Closure, Fusion Compiler, Synopsys DSO.ai, Sub-3nm device physics, primetime, Dynamic IR drop, Crosstalk challenges, Flows-as-Code, Standard Cell SRAM library architectures, Tape-out experience with TSMC N3, CPU micro-architecture, Cerebrus, IC Compiler II, Synopsys Fusion Design Platform

Power gating and retention strategies, Signal Integrity Analysis, Power Planning, ASIC SoC physical design, Leakage optimization and dynamic power reduction, UPF CPF-based low-power implementation flows, Timing Closure, Physical Verification and Signoff, Advanced low-power architectures, Clock gating methodologies, Adaptive power management techniques, Floor planning and Partitioning, Power-aware physical design and implementation closure, Placement and Optimization, Routing and Congestion Analysis