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Showing 3 jobs
Skills:
power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity
Skills:
Hierarchical design implementation, Feed-through planning, PnR implementation, PV clean-up, SoC Full-chip floorplanning, PG creation and push-down methodologies, Scripting flow deployment, Physical Verification, RDL knowledge, Sta, Die file generation
Skills:
Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation
