Physical Design, Timing Closure, Power Planning, Deep sub-micron technology issues, Floor Planning, Signal integrity analysis, Place And Route

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification

Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting

redhawk , Innovus, primetime, Synthesis, Physical Design, tapeout

Synthesis, Scripting automation, EDA Tools, Mixed signal complex IPs, AI and AI-enabled workflows, Critical paths of multi-GHz builds

power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity

IR EM Analysis, SI PI Analysis, Floorplanning and Power Planning, Physical Verification, STA and Timing Closure, Low Power Design UPF CPF, Physical Design and Signoff, Tcl Python Scripting, Advanced Node Design Methodologies, Clock Architecture and CTS, AI-assisted Design Flows

Shell, Perl, Python, Tcl, Ecos, Flows, automation, Innovus, primetime, ICC2, Tempus, FusionCompiler, Design Reviews, EM closure, Ir, PD methodologies, tapeout readiness, RTL-to-GDSII flow, Timing Closure, Si, PPA optimization