System Verilog, Building test benches from scratch, Data path verification performance tests, Gate level simulation, ASIC verification using UVM, formal verification

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Python, Tcl, OCV, primetime, Low-Power UPF, SI Crosstalk, CRPR, Cadence Tempus, MMMC, Eco, POCV, SDC Constraints, CPF, AOCV, LVF

Debugging, System Verilog, UVM based verification, Problem-solving skills, ARM bus protocols

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus

shielding , Tcl Scripting, Perl, Layout dependent effects, Signal shielding, Semiconductor device physics, Cadence Virtuoso XL VXL, Latchup, Skill, Parasitic noise, Calibre, EMIR, Noise isolation, Esd, Supply consideration, Isolation, Well’s substrates, Layout matching, Double patterning, Device matching

static timing analysis, System Verilog, hardware modeling, lint checks, Verilog V2K, logic debug environments, high-frequency optimization, power aware design, UPF, Rtl Design, low-power logic design, Cross-clock domain crossings

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs