System Integration, Matlab, Signal Grounding, Monte Carlo Analysis, Physical Layout Management, Top-level Verification, Block-level Modeling, AMs, Post-layout Parasitic Extraction, Architectural Tradeoff Analysis, Block-level Topology Selection, IC System Partitioning, Spectre, Worst-case Identification, Schematic Generation, Simplis, Routing Tradeoffs, Device Physics Knowledge

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings