EDA tool chain - FusionCompiler, Shell, Perl, Python, Tcl, Hold Setup Requirement, floorplanning, Signoff Checks, IP integration, Make flow, Timing Fixture, Synthesis, Physical Verification, Power Intent spec and checks, Extraction, script programming, DRV checks, Tk, Physical Design Implementation, Place And Route, Clock Tree Synthesis

Perl scripting, Tcl, Cadence EDI, Mentor Calibre, Synopsys ICC, Design Automation

Python Scripting, Tcl Scripting, Calibre, Timing Closure, Automation scripts, Physical design implementation, primetime, Cadence Innovus, Tempus, Synopsys ICC2, SDC constraint management

routing, IC backend flow, APR flow, floor-planning, Pv, Physical design flow, Placement, CTS, Sta

Cadence, Physical Layout design, EDA tool Synopsys, Mentor

Shell, Python, Tcl, Physical Design, floorplanning, Cadence Innovus, Low-power design methodologies, Synopsys ICC2

Tcl Scripting, Timing Closure, Tempus, OCV effects, DMMMC flow, noise crosstalk