C, Linux, Perl, Verilog, Python, Uvm, systemverilog

Computer Architecture, Digital Analog circuit design, Place Route flows, Sta, SCL characterization, ASIC Synthesis, Microcontroller, TSMC SCL N7 vs N6, Physical Verification, Standard Cell Library development, LVS, Physical design flows, Linux Unix environment, CMOS Circuit theory, PNR, Digital analog systems, DRC, Simulator Design Verification, Microprocessor, device physics

C, Python, high-speed interfaces, AI-assisted tools, Uvm, systemverilog

Verilog, Asm, Tcl, coverage judgement, Verdi, Indago, Functional Safety ISO26262, Uvm, AMBA protocol AHB, systemverilog, C Language, Vplan verification plan making, Formal verification SVA, assembly, XLM

synopsys primetime , Hdl Languages, Shell, PERL, Verilog, Scripting Languages, Tcl, Synthesis, cdc, floor-planning, ASIC implementation, Cadence Innovus, LEC, Timing Analysis, Place And Route, Cadence Tempus, Genus, Timing Closure, ARMv9