Software Release Management, Shell scripting, WLAN standards IEEE 802.11, Deployment Git, Automation using Python

C, Perl, Arm, Python, RISC-V Assembly, digital Verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi