Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

Perl scripting, System Verilog, Python, PPA optimization, Cadence Innovus, advanced-node Block SoC designs, RTL-to-GDS implementation

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

power integrity , Tcl, Python, Perl, Shell, Physical Design signoff, Ansys RedHawk, Cadence Voltus, IR EM analysis

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols