C, Digital Signal Processing, Perl, Python, ASIC design flow, Cadence, digital design and verification methodologies, Uvm, systemverilog, EDA Tools, Mentor Graphics, Synopsys

prevalent standards Protocols viz. PCIe Gen3 4 5 USB3 DDR4 5 Ethernet CSI2 I3C AMBA, Scripting, bug analysis, Verification closure, Full chip test plan development modification, Regressions coverage analysis, OVM UVM methodologies using SV, ASIC SoC life cycle, Testbench development modification, Gate level simulations, Test case development coding execution

C, Digital Signal Processing, Perl, Python, ASIC design flow, digital design and verification methodologies, Cadence, Uvm, systemverilog, EDA Tools, Mentor Graphics, Synopsys

C, Verilog, Asm, Tcl, Verdi, Indago, Functional Safety ISO26262, Uvm, AMBA protocol AHB, systemverilog, C Language, Vplan verification plan making, Formal verification SVA, assembly, XLM

Mac, C, Verilog, formal verification, PHY, Ethernet Protocol, Ethernet switch, mixed-signal co-simulation, systemverilog