semiconductor process technology , Perl, Scripting Languages, Python, Tcl, ASIC design flow, physical design strategies, Cadence, EDA Tools, Mentor Graphics, Synopsys, low-power design techniques

Python Scripting, Tcl Scripting, primetime, ICC2, Tempus, LVS, SDC constraint management, FinFET technology, Physical Design, Calibre, Innovus, DRC

rc extraction , Synopsys, Power and Noise Analysis, Physical Verification, ARMv8, Calibre, Floor-planning, Cadence, Signal Integrity, Physical Design, Clock Tree Synthesis, Place And Route, FinFET Technology, Timing Closure

Cadence, Physical Layout design, EDA tool Synopsys, Mentor

EDA tool chain - FusionCompiler, Shell, Perl, Python, Tcl, Hold Setup Requirement, floorplanning, Signoff Checks, IP integration, Make flow, Timing Fixture, Synthesis, Physical Verification, Power Intent spec and checks, Extraction, script programming, DRV checks, Tk, Physical Design Implementation, Place And Route, Clock Tree Synthesis