C, Perl, Python, ASIC design flow, digital design and verification methodologies, Uvm, systemverilog

C, Digital Signal Processing, Perl, Python, ASIC design flow, digital design and verification methodologies, Cadence, Uvm, systemverilog, EDA Tools, Mentor Graphics, Synopsys

Python, I2c, Jtag, Uart, SMBus, MDIO

prevalent standards Protocols viz. PCIe Gen3 4 5 USB3 DDR4 5 Ethernet CSI2 I3C AMBA, Scripting, bug analysis, Verification closure, Full chip test plan development modification, Regressions coverage analysis, OVM UVM methodologies using SV, ASIC SoC life cycle, Testbench development modification, Gate level simulations, Test case development coding execution

DDR, Usb, Perl, Pcie, Verilog, Python, Tcl, CDNS EDA tool, Uvm, systemverilog

object detection , Computer Vision, C, Image Processing, Tensorflow, Pytorch, Linux, Opencv, Python, Perception pipelines, Isaac Sim, Gazebo, reinforcement learning, Tracking, embedded solutions, Hardware-software co-design, AI ML models, Arm Cortex-A, RZ SoCs, ROS2, Real-time systems