power integrity , MATLAB, Python, Signal Integrity, schematic capture, high-speed PCB design

Ethernet, Scripting, CSI2, Test case development coding execution bug analysis, Testbench development modification, Verification closure, AMBA, Gate level simulations, PCIe Gen3 4 5, DDR4 5, Regressions coverage analysis, ASIC SoC life cycle, USB3, Full chip test plan development modification, I3C, OVM UVM methodologies using SV

Mac, C, Verilog, formal verification, PHY, Ethernet Protocol, Ethernet switch, mixed-signal co-simulation, systemverilog

C, Digital Signal Processing, Perl, Python, ASIC design flow, Cadence, digital design and verification methodologies, Uvm, systemverilog, EDA Tools, Mentor Graphics, Synopsys

Verilog, Asm, Tcl, Vcs, Verdi, Indago, Uvm, systemverilog, C Language, Vplan verification plan making, assembly, XLM, coverage judgement, Axi, APB, ISO26262, AMBA protocol, Functional Safety, AHB, formal verification, SVA