Ovm, System Verilog, AMBA AXI, Uvm, CHI protocols

Ethernet, Scripting, CSI2, Test case development coding execution bug analysis, Testbench development modification, Verification closure, AMBA, Gate level simulations, PCIe Gen3 4 5, DDR4 5, Regressions coverage analysis, ASIC SoC life cycle, USB3, Full chip test plan development modification, I3C, OVM UVM methodologies using SV

Test Case Creation, Ethernet, Scripting, gate-level simulations, coverage analysis, ASIC SoC development lifecycle, OVM UVM methodologies, CSI2, testbench development, UCIe, systemverilog, coding execution, verification sign-off, AMBA, regression runs, PCIe Gen3 4 5, DDR4 5, USB3, bug investigation, I3C, full-chip test plans

C, Verilog, Python, Perl, Linux, Uvm, systemverilog