Perl scripting, Tcl, Cadence EDI, Mentor Calibre, Synopsys ICC, Design Automation

Cadence, Physical Layout design, EDA tool Synopsys, Mentor

Tcl Scripting, Timing Closure, Tempus, OCV effects, DMMMC flow, noise crosstalk

EDA tool chain - FusionCompiler, Shell, Perl, Python, Tcl, Hold Setup Requirement, floorplanning, Signoff Checks, IP integration, Make flow, Timing Fixture, Synthesis, Physical Verification, Power Intent spec and checks, Extraction, script programming, DRV checks, Tk, Physical Design Implementation, Place And Route, Clock Tree Synthesis

Formality, static timing analysis tools, block-level PnR, LEC, Cadence Genus, Physical Design, Fusion Compiler, PrimeRail, Calibre, Innovus, primetime, Tempus, IC Compiler, Voltus