rtl development , System Verilog, Dsp, Verilog, static timing analysis, Matlab, Perl, Pcie, Unix Shell, UCIe, Functional Verification, fec, Vlsi Design

hardware description language , C, Nvme, PERL, Pcie, Verilog, Python, Tcl, scripting programming language, On-Chip bus protocols, UVM based test bench, systemverilog, Rtl Design, Timing Closure, Axi, APB, UAlink, CXL, coverage closure analysis, AHB, Lint CDC check

Tcl, Perl, Cadence, Synopsys, C-Shell, Mentor