C, Perl, Python, ASIC design flow, digital design and verification methodologies, Uvm, systemverilog

Linux Environment, Digital signal processing concepts, Mathematics

Simulation Debugging, Simulation Coverage Analysis, Netlist Timing SDF, Verification Strategy, Testbench Development, Test Plan Development, Documentation and Reporting

prevalent standards Protocols viz. PCIe Gen3 4 5 USB3 DDR4 5 Ethernet CSI2 I3C AMBA, Scripting, bug analysis, Verification closure, Full chip test plan development modification, Regressions coverage analysis, OVM UVM methodologies using SV, ASIC SoC life cycle, Testbench development modification, Gate level simulations, Test case development coding execution

DDR, Usb, Perl, Pcie, Verilog, Python, Tcl, CDNS EDA tool, Uvm, systemverilog