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Synopsys Inc

Verification Senior Engineer

Early Applicant
  • 5 months ago
  • Be among the first 50 applicants
Exp: 4-6 Years

Semiconductor Manufacturing

Job Description

Job Description And Requirements

Our Digital Team is seeking for great Design Verification engineer. Join with us if you are finding a job which challenge yourself with latest process technologies.

Opportunities

  • SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team.
  • Professional, innovative, fair and fun working environment.
  • Competitive salary and benefit such as health Insurance, Football, Table tennis, Badminton, Yoga, Zumba Clubs.
  • Team building activity: Team trip, Family Day
  • Opportunity to work with the complete design flow for a complicated Analog Mixed Signal Design from specification to silicon.
  • Clear career path of self-development to either Technical Experts or Manager
  • Travel to USA, Europe and Asia for training or on-site support.

Job Descriptions

  • Work in the RnD team to develop and validate for the high-bandwidth interface IP.
  • Test planning, checklist, Coverage and Assertion planning
  • Hands on experience in creating detailed Verification Environment from Functional Specifications
  • Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
  • Writing test cases, checkers, and coverage plan and verification plan.
  • Debug of simulations, including those of real signals modeled using SV for analog.
  • RTL, GLS & Co-simulations & coverage closure
  • Take part in technical reviews and contribute closely.
  • Take part in customer support with bring-up of IP in customer simulation environment.
  • Follow and improve development process ensuring high quality output.

Skills Requirements:

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 4+ years of experience in Design Verification
  • Experience in skill with design tools: VCS, Verdi. Familiar Formal verification tool (vc_formal) is a plus.
  • Knowledge of UPF, UVM (Universal Verification Methodology) and SVA (System-Verilog Assertion)
  • Excellent debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus.
  • Accountable, result oriented and good English communication.
  • Great team player, willing to support others.
  • Self-motivated and enthusiasm in technology and solving problems.

Job Category

Engineering

Country

Viet Nam

Job Subcategory

ASIC Digital Design

Hire Type

Employee

More Info

Skills Required

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Date Posted: 10/06/2024

Job ID: 81330743

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