Staff Digital Design Engineer

Staff Digital Design Engineer

Marvell Technology, Inc.
Not Specified
Not Specified

Job Description


About Marvell
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The Opportunity
Marvell is the leader in data movement interconnects between and inside these data centers. We move big data fast, around the globe, with high quality and reliability. We offer semiconductor components and optical subsystems to our networking original equipment manufacturer (OEM), optical module, cloud and telecom service provider customers.
We are very focused on our customers success, providing them higher quality products. We develop innovative products and leading-edge solutions that help our customers connect hundreds of thousands of computers servers inside a data center as well as hundreds thousands of data centers around the globe. We believe that 'The Data Center Is the Computer™' and 'The Cloud is the Network™.' At Inphi, our solutions help our customers make that vision of tomorrow a reality today. Join us and move fast as a member of our team!
Key Responsibilities:

  • Define & design RTL for ASIC/ FPGA/CPLD with Verilog language

  • Write documents related to your design

  • Be responsible for debugging for your design (if any)

  • RTL self-test on demand

  • Simulation and On-Board debug

  • Synthesis and Timing Closure for your RTL if requested

  • Frequently update your task status on ZOHO/CODENDI/Mail, etc…

  • Complete Tasks which assigned by your group leader on time and quality.

  • Other related tasks assigned by Leader/ Superior

  • Work with design team to RTL code implementation for next generation Mixed-Signal, high speed CDR products.

  • Work with backend engineers on post-layout timing closure.

Job Requirements:

  • BS/MS in Telecommunication/Electric-Electronics

  • Good problem solving & communication skills.

  • Good English Reading/Speaking skills.

Preferred:

  • Experience in Design for transport/Serdes chips, especially for IEEE802.3 PCS/PMA layers from 1G up to 400G

  • Verilog, System Verilog

  • Familiar with script languages: Python, Perl, C-Shell, Bash-Shell, TCL, etc.Knowledge of ASIC chip design flow

  • Familiar with Linux working environment.
The Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Job Details

Employment Types:

Industry:

Other

Function:

IT

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