Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Azure, AWS, Cloudformation, Security Groups, Terraform, Gcp, Vpn, Direct Connect, ExpressRoute, NSGs

Strategic technical decision-making, Cross-team technical leadership, Enterprise data platform architecture, Cloud-native design, Streaming and distributed processing systems, Large-scale system architecture design, Infrastructure-as-code, Evaluating and modernizing platform capabilities

Shell Scripts, Sql, Aws

arm architecture , Uart, Pcie, Verilog, I2c, Flash, low power methodology, system debug infrastructure, RTL level checks, digital ASIC design, systemverilog, SSP, AMBA bus protocols, system memory hierarchy, constraints development, ARM based ecosystem components, multi-core SOC designs, DRAM, ARM v8 and v9 specifications, DC DC-T based synthesis

Java, Golang, Gcp, Docker, Azure, Python, AWS, backend distributed systems

Python, Typescript, OpenAI API, Anthropic Claude API, Playwright

AWS, Pki, Dns, Golang, Http, DHCP, Tls, Kubernetes, Python, Azure, Ha, Docker, Gcp, Vpn, OVA

Devops, Spring Framework, Agile, Aws Ec2, Java, Jira, Jenkins, Git, CI CD, microservice architectures