Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Verilog, Tcl, System Verilog, Python, Perl, CHI, UVM-based testbenches, Mentor Questa, Ace, AMBA, Synopsys VCS, VHDL, RISC-V instruction set architecture, APB, Axi, Cadence Xcelium

Embedded Firmware, Verilog, Scripting Languages, System Verilog, DVFS, DCVS, power gating, clock gating, power management verification, UPF, C Language, reliability throttling