clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

Physical Design, Physical Design Engineer, Automation script

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

C, Tcl, Routing, Perl, Physical Verification, LEC, Calibre, Innovus, floorplanning, EDA Tools, Clock Planning, ICC2, primetime, Placement, Timing Closure, Physical Design Implementation

Physical Design, DFT Implementation, Layout Extraction, Rtl Design