perl scripting, python, Tcl, Sta, PNR, power integrity analysis tool, Synopsys Redhawk SC, EM IR and PDN domain, Cadence Voltus

C, Verilog, automation, Scripting, coverage closure, AI-assisted workflows, RTL testbench debugging, Uvm, systemverilog

Vcs, Tcl, Python, Perl, Testbench Architecture, Questa, Uvm, Functional Coverage, systemverilog, CHI, Ace, Xcelium, Constrained Random Verification, RISC-V architecture, Verdi, SVA, DVE, Axi

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming