Pli, Systemc, ProtoCompiler, hardware emulation, Cadence Z3, Simulators, Siemens Veloce, FPGA prototyping, Xilinx Vivado, Synplify Premier, Synopsys ZeBu, SV Verilog, Emulators, dpi

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

Embedded C Verification., Cryptography Algorithms, SoC Verification, Uvm, systemverilog, ARM Cortex M4

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog