C, Pli, Systemc, hardware emulation, ProtoCompiler, Cadence Z3, Simulators, Siemens Veloce, FPGA prototyping, Xilinx Vivado, Synplify Premier, Synopsys ZeBu, SV Verilog, Emulators, dpi

Usb, perl, C, Pli, Pcie, Python, Systemc, hardware emulation, ProtoCompiler, Cadence Z3, Simulators, CHI, Siemens Veloce, FPGA prototyping, Xilinx Vivado, Synplify Premier, Synopsys ZeBu, CXL, SV Verilog, NVLINK, CPU-GPU coherency, Emulators, dpi

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC