bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

System Verilog, C, Bug Tracking Tool, Git, Models for performance verification, Synopsys, Monitors, Transactors, Performance test plan development, Cadence, RTL simulations

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi