Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

synopsys primetime , Tcl, Python, Perl, AOCV, place-and-route, timing exceptions, Extraction, CTS, OCV, clocking methodologies, SI noise analysis, Synthesis, MMMC methodologies, ECO implementation, POCV

cdc, Dft, Synthesis, DV debug, Debug, RTL Coding, Silicon Bring up, Rtl Design, ip design

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Cadence, Mentor, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

control logic , Processor microarchitecture, CPU datapath expertise, Physical design implementation, ALUs, Execution units, Block-level tape-outs, FPUs, RTL to GDS implementation, Data-paths, High-speed digital logic