Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Usb, System Verilog, Jtag, Ethernet, Python, Pcie, Perl, TSN, UVM methodology, SoC architecture verification, scripting in Linux Unix environments, High speed USB, Design for Debug, ARM based SoC verification

Debugging, Uvm, Test Planning and Strategy, systemverilog, Mixed-Signal Verification

ARM M-series core operations, DMA interrupt handling, Debugging using disassembly and Tarmac for ARM cores, C code for ARM processors, UVM testbench development, Cache and interconnect, Cadence simulators and SimVision, Cadence and Synopsys VIPs, AHB and APB interface protocols

Verification IP (VIP), Bus Functional Model (BFM), Pcie, systemverilog, Uvm, UCIe, Protocol Verification, UVM Testbench Development, Synopsys VCS, Verdi