Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Rtos, Embedded Linux, Uart, Spi, Git, Ipc Mechanisms, I2c, C Programming, Python, BACnet, Modbus, Linux process management

arm architecture , Verilog, Device Drivers, C, Systemc, AHB, FPGA prototyping, systemverilog, Zephyr RTOS, RISC-V, register-level firmware, APB, Axi, hardware software interfaces, hardware emulation environments, Veloce, BUS Protocols, RTL, HALs, Embedded Linux kernel driver development, TLM 2.0, register maps, DMA, interrupt handling, Palladium

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

Verilog, Tcl, Ethernet, Perl, C, Scripting Languages, Pcie, AHB, Flash interfaces, RDC constructs, IP Synthesis, IP development flow, QuadSPI, FPGA Emulation Board, Axi, SERDES, BUS Protocols, HDLs, DDR4, High Speed Serial protocols, ATPG, cdc, AMBA, Testplan development, VHDL, microcontroller architecture, pre silicon validation, LPDDR4, Dft

rtl development , nand flash , Tcl, Verilog, FPGA Design, Python, Bash, Pcie, IP Integrator, Vivado Design Suite, VHDL, ChipScope ILA, Embedded Systems, Xilinx FPGAs

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Vcs, Pcie, Verilog, Debugging, Python, Scripting, Bash, Digital Logic Design, FPGA Design, Ethernet, Tcl, high-speed interfaces, Xcelium, Simulation Tools, FPGA synthesis, LPDDR4, Altera Quartus Prime Pro, LPDDR5, systemverilog, Axi, Timing Closure, Questa, CXL, DDR5, DDR4