C, Python, high-speed interfaces, AI-assisted tools, Uvm, systemverilog

C, Digital Signal Processing, Perl, Python, ASIC design flow, digital design and verification methodologies, Cadence, Uvm, systemverilog, EDA Tools, Mentor Graphics, Synopsys

Verilog, Asm, Tcl, coverage judgement, Verdi, Indago, Functional Safety ISO26262, Uvm, AMBA protocol AHB, systemverilog, C Language, Vplan verification plan making, Formal verification SVA, assembly, XLM

prevalent standards Protocols viz. PCIe Gen3 4 5 USB3 DDR4 5 Ethernet CSI2 I3C AMBA, Scripting, Regressions coverage analysis, Verification closure, Full chip test plan development modification, ASIC SoC life cycle, OVM UVM methodologies using SV, Testbench development modification, Test case development coding execution bug analysis, Gate level simulations